In field of semiconductor power devices, it is desirable to further reduce Qgd (charge between gate and drain) for less power consumptions and higher switching speed, for a trench MOSFET (Metal Oxide Semiconductor Field Effect Transistor), such purposes are generally achieved by implementing a thick trench bottom oxide in trenched gates of the trench MOSFET. Meanwhile, it is also desirable to simplify the manufacturing processes in forming the trench MOSFET having thick trench bottom oxide mentioned above for requirement of mass-production.
FIG. 1 shows a trench MOSFET 100 of prior art having thick trench bottom oxide disclosed in U.S. Patent No. 20080265289 which has a high-density plasma (HDP, hereinafter) CVD oxide 115 on bottom of trenched gates for reduction of Qgd, and has a HDP oxide 120 on top surface of mesa area between adjacent trenched gates as implanting-ion block mask for saving body and source masks during manufacturing processes. However, the trench MOSFET 100 and the manufacturing method of prior art still encounter difficulties and limitations for device shrinkage and gate charge reduction. First, a high interface state gate charge is induced between the HDP oxide 115 and the bottom of the trenched gates. Second, planar source-body contact is used in the trench MOSFET 100 of prior art, limiting device cell shrinkage as the planar source-body contact occupying large space and causing poor contact performance. Furthermore, a trade-off between a space Sbs (the space defining P body and n+ source regions, as illustrated in FIG. 1) and thickness of the HDP oxide 115 causes a difficulty in optimization of device performance because the both are determined by wet etching time for removal of trenched gates sidewall oxide in manufacturing processes. The longer Sbs, the thinner the HDP 115 resulting in higher Qgd; the shorter Sbs, the less n+ source regions formed into the P body regions resulting in less contact area to source metal 160, leading to high contact resistance and poor contact performance.
Besides, the source metal 160 and gate metal 106 must keeps a space of at least 3.0 um to avoid metal bridging issue during metal etching process. In order to form an inverted V shape P body profile in middle of two adjacent trenched gates, the junction depth of the P body regions must be kept greater than 1.0 um along the trenched gates, causing high gate charge Qg. On the other hand, if the P body regions have shallow junction depth, the termination area (as illustrated in FIG. 1) will not work because the P body region in the termination area can not connect to the P body region in the active area (as illustrated in FIG. 1).
Meanwhile, near the trenched gate in gate contact area, which is positioned between the termination area and the active area, additional parasitic bipolar transistor with floating n+ source regions is built, causing poor avalanche capability because the parasitic bipolar transistor is easily turned on. Moreover, the termination area comprises guard rings having separated P body regions, which will result in early breakdown in middle of two adjacent trenched gates during the trench MOSFET 100 is reverse biased.
Accordingly, it would be desirable to provide a new and improved configuration and fabricating method for a semiconductor power device having low gate charge, high breakdown voltage and reduced cell pitch without complicating the process technology.